TSMC is also one of the world-famous chip manufacturers. If we talk about a small Process Node, the name TSMC appears as the first name. Most recently, TSMC released Transcript for the quarterly results. There is also interesting information. Essentially, it has been confirmed that mass production of 5nm chips will be in the table for the 2nd quarter of 2020, and that production scale has already begun.
It is reported that the risk trial yield has reached 50% and the production capacity is expected to double. According to the data released by Dr. C. C. Wei (President and Co-Chief Executive Officer), the 5nm process has been completed and is currently undergoing risk trial production. The mass production time is also advanced to the Q1 quarter next year. This time is about one quarter ahead of the normal mid-year mass production.
According to sources from the supply chain, the yield of the 5nm risk trial production period has reached 50%, which is much smoother than the previous advanced technology trial production. Over time, the yield of the 5nm process will gradually increase, especially during the mass production phase.
Not only yield satisfactory, but TSMC 5nm technology capacity has also grown dramatically, initially expected only a month 4.5 million wafers, after rising demand because the way rose to 5, 7 million pieces per month which may eventually reach 8 million. The production capacity of 10,000 wafers has almost doubled.
The 5nm capacity increase is also related to the high market demand. At present, it can be determined that there will be Apple and Huawei Hisilicon in the 5nm process. These two are the earliest starters. Apple’s A14 and Huawei Kirin 1000 (tentative name) are early. In September of this year, the 5nm film was completed and the progress is also the fastest.
Subsequent AMD ‘s Zen4 processor, Qualcomm’s SD 875, and Xilinx’s next-generation FPGA are also expected to use the 5nm process of TSMC, but the progress is later than the previous two.
According to official data, compared to 7nm (first generation DUV ), the new 5nm chip based on Cortex A72 core can provide 1.8 times the logic density, a speed increase of 15 %, or power consumption by 30 %, the same process SRAM is also very Excellent and reduced in area.
In addition, in July this year, TSMC announced an enhanced version of the N5P, which is also optimized for front and rear lines, which can bring 7% performance improvement under the same power consumption, or reduce power consumption by 15% at the same performance.
Another point is that TSMC’s 5nm node will also fully use the EUV process. Compared to the 7nm EUV process, only 4 layers of EUV masks will be used. The 5nm EUV process will increase the number of mask layers to 14-15 layers, making the EUV process more efficient.
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